1. Field of the Invention
The present invention is directed to a register formed by a D type flip-flop with the data of each input line being loaded into a flip-flop memory element by an appropriate load control which is triggered by the edge of an applied load control input signal associated with each input line. The register uses no transmission gates, either in input or in output and one flip-flop memory element, regardless of the number of the input lines. It may have auxiliary Clear and Reset inputs, and in this case the memory element will respectively behave as an ordinary RS flip-flop.
The register is particularly useful in the construction of "self-clocking" or "self-timing" asyncronous digital circuits.
2. Discussion of the Prior Art
A conventional register having one or more input lines I.sub.n coming from n information sources with which suitable load control input instructions Ld.sub.n are associated is illustrated in FIG. 1. The load control input instructions Ld.sub.n cause a selected input vector I.sub.n to be transferred to the register output Q.
Generally, according to the methods known in the art, such a register can be constructed in two ways. In the first, shown in FIG. 2, a plurality of individual registers Re.sub.n are associated with the I.sub.n input vectors, the outputs of which are connected to register output Q through a plurality of transmission gates tg.sub.n. In this case the exchange of input data to the output Q occurs downstream of the registers Re.sub.n.
In order to ensure an independence of the active level of the latest load control signal Ld.sub.i (1.ltoreq.i.ltoreq.n) from previous load control signals an arbiter 11 is used which chronologically enables only the transmission gate tg.sub.i associated with the register Re.sub.i in which the last storage took place, in response to a significant switching edge of the related load input load control signal Ld.sub.i.
The second way in which the FIG. 1 register is typically implemented is shown in FIG. 3. Here, the access of I.sub.n information sources to a single Re register is controlled by the transmission gates tg.sub.n which are respectively connected to the input vectors I.sub.n. The selected information will be stored in register Re by the significant edge of the load input control signal Ld.sub.i. In this case the information exchange is located before the register Re and the output of the register Re is taken as the output Q. In this case, as well, the independence of the active level of the last load signal as compared with prior load signals requires the utilization of an arbiter 11 which chronologically enables only the transmission gate associated with the latest storage control input Ld.sub.i. The actual storage of the information, now present on the inside bus, will occur in the Re register only when the information is stabilized. To enable this, the load input control signal Ld.sub.n will accordingly delays be applied to register R.sub.e through a time operator T which delays the latest applied control Ld.sub.i for a period sufficient to allow the information I.sub.n to stabilize. The delay will be controlled by a clock, the time of which is determined only and exclusively on the basis of statistical information.
Both of the FIGS. 2 and 3 circuits require a complex arbiter 11 and for FIG. 3 a clock controlled delay to ensure proper timed operation of the FIG. 1 register.